1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a mode control circuit for controlling a specific mode of a semiconductor device and to a semiconductor memory device having the mode control circuit.
2. Description of the Related Art
Upon completion of the manufacture of a semiconductor device, a testing process is commonly performed for determining whether the semiconductor device operates normally. Those semiconductor devices that are determined to function normally are sold to users and those that are determined to be defective are discarded. However, it is impossible to test for the possibility of defects in all functions of the semiconductor device in the testing process. Thus, a separate test mode for more effectively testing the semiconductor device is included in the testing process.
Operations or functions that are different from normal operations stipulated in the specification of the semiconductor device can be included in the test mode. In a case where the user enters the test mode for any reason during use of the semiconductor device, errors occur in the system in which the semiconductor device is mounted. Thus, semiconductor devices are commonly designed to protect the test mode to prevent or deter entry into the test mode. Nevertheless, if the user unexpectedly enters the test mode while using the semiconductor device, errors can occur in the system employing the semiconductor device.
To address the above problems, it is a first object of the present invention to provide a mode control circuit for a semiconductor device which is capable of preventing the semiconductor device from entering a specific mode and in which a producer (or worker) can allow the semiconductor device to enter the specific mode if necessary, even by an end user of the semiconductor device.
It is a second object of the present invention to provide a semiconductor memory device having the mode control circuit.
Accordingly, to achieve the first object, there is provided a mode control circuit for a semiconductor device. The mode control circuit includes a mode entrance portion for outputting an output signal in response to an external control signal, a mode entrance control portion for generating a mode entrance enable signal for controlling the entry by the semiconductor device into a specific mode of operation, and a logic portion for logically combining the output signal of the mode entrance portion and the mode entrance enable signal to generate a mode signal for setting the specific mode. The mode entrance control portion includes a first fusing portion including a first fuse, a second fusing portion including a second fuse, and a mode entrance control signal generating portion for activating the mode entrance enable signal in a first case where the first and second fuses are maintained at an initial state or are changed from the initial state, and deactivating the mode entrance enable signal in a second case where only one of the first and second fuses is changed from the initial state.
It is preferable that the initial state of the first and second fuses is a state where at least one of the first and second fuses are closed, and the state where the first and second fuses are changed at the initial state is a state where at least one of the first and second fuses are open.
It is also preferable that the first and second fuses can be changed from the initial state following packaging.
It is also preferable that the specific mode is a test mode for testing the electrical functions of the semiconductor device.
It is also preferable that the first and second fusing portions are operated in response to a power-up signal which is increased to a predetermined voltage and is decreased to a null voltage, respectively, when supply voltage is applied to the semiconductor device.
In order to achieve the second object, there is provided a semiconductor memory device. The semiconductor memory device includes first and second pads for inputting an external control signal and data, a mode control circuit for outputting a mode signal for deciding a specific mode of operation of the semiconductor memory device in response to the control signal input through the first pad, and an internal circuit for processing data input through the second pad according to the mode signal. The mode control circuit includes a mode entrance portion for outputting an output signal in response to the control signal, a mode entrance control portion for having a first fusing portion including a first fuse, a second fusing portion including a second fuse, and a mode entrance control signal generating portion for activating a mode entrance enable signal in a first case where the first and second fuses are maintained at an initial state or are changed from the initial state, and deactivating the mode entrance enable signal in a second case where only one of the first and second fuses is changed from the initial state, to generate the mode entrance enable signal for controlling the semiconductor device to enter the specific mode, and a logic portion for logically combining the output signal of the mode entrance portion and the mode entrance enable signal to generate a mode signal for setting the specific mode.
It is preferable that the specific mode is a test mode for testing electrical functions of the semiconductor device.
It is also preferable that the internal circuit operates in the specific mode when the mode signal is activated and operates normally when the mode signal is deactivated.
According to the present invention, a user is prevented from entering a specific mode, for example during end use of the semiconductor device, and the semiconductor device can later regain entry into the specific mode, for example by a manufacturer by a producer, if desired.